wishbone: fix SRAM; improve tests for Decoder & Arbiter wishbone_interconnect
authorHarry Ho <hh@m-labs.hk>
Sun, 1 Mar 2020 04:17:10 +0000 (12:17 +0800)
committerHarry Ho <hh@m-labs.hk>
Sun, 1 Mar 2020 04:17:10 +0000 (12:17 +0800)
commit46e37604497be0c26aa807b54d74c50e156b043a
treeceaa78cb38c47d403d7518e35be897f4f713ae75
parentbe14bdab3d7837ec8ba5aefd9b3441ede33f03a8
wishbone: fix SRAM; improve tests for Decoder & Arbiter
nmigen_soc/test/test_wishbone_bus.py
nmigen_soc/wishbone/sram.py