vendor.lattice_{ecp5,machxo_2_3l}: remove -forceAll from Diamond scripts.
[nmigen.git] / examples /
2020-11-06 whitequarkexamples: clean up oudated code.
2020-08-27 whitequarksim: split into base, core, and engines.
2019-12-02 whitequarkhdl.ast: actually remove simulator commands.
2019-11-28 whitequarkback.pysim: redesign the simulator.
2019-10-26 whitequarkback.rtlil: fix lowering of Part() on LHS to account...
2019-10-11 whitequarkhdl.ast: deprecate Signal.{range,enum}.
2019-10-09 whitequarkexamples: update blinky, add some explanatory text...
2019-09-23 whitequarklib.cdc: MultiReg→FFSynchronizer.
2019-09-08 whitequarkhdl.mem,lib,examples: use Signal.range().
2019-09-06 whitequarkRemove nmigen.lib from prelude.
2019-08-22 Reto Kramerexamples/basic/uart: document `divisor` parameter.
2019-08-12 whitequarkhdl.xfrm: CEInserter→EnableInserter.
2019-07-08 whitequarktest: generate examples to verilog as part of unit...
2019-07-08 whitequarkexamples/basic/ctr_ce: fix outdated syntax.
2019-06-27 whitequarkexamples: add concise UART example.
2019-06-04 whitequarkvendor.board: split off into nmigen-boards package.
2019-06-03 whitequarkexamples: reorganize into examples/basic and examples...
2019-06-03 whitequarkvendor.board: extract package.
2019-06-03 whitequarkbuild.res: if not specified, request resource #0.
2019-06-01 whitequarkvendor.ice40_hx1k_blink_evn: implement.
2019-04-21 whitequarkRemove examples/tbuf.py.
2019-04-21 whitequarkhdl.ir: detect elaboratables that are created but not...
2019-03-12 Alain Péteutexamples.por: fix typo
2019-01-26 whitequarkexamples: update for newer API.
2019-01-26 whitequarkhdl.ir: rename .get_fragment() to .elaborate().
2019-01-14 whitequarklib.io: lower to platform-independent tristate buffer.
2019-01-14 whitequarkhdl: make ClockSignal and ResetSignal usable on LHS.
2018-12-28 whitequarkhdl.rec: add basic record support.
2018-12-27 whitequarkhdl.dsl: add support for fsm.ongoing().
2018-12-26 whitequarkexamples: add an FSM usage example (UART receiver).
2018-12-23 whitequarkcli: new module, for basic design generaton/simulation.
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa...
2018-12-21 whitequarkback.rtlil: implement memories.
2018-12-20 whitequarkir: allow non-Signals in Instance ports.
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters...
2018-12-17 whitequarkback.rtlil: implement Array.
2018-12-15 whitequarkexamples: rename clkdiv/ctrl to ctr/ctr_ce.
2018-12-15 whitequarkMove star imports to make `from nmigen import *` usable.
2018-12-14 whitequarkback.pysim: Simulator({gtkw_signals→traces}=).
2018-12-14 whitequarkback.pysim: more general clean-up.
2018-12-14 whitequarkback.pysim: if requested, write a gtkw file with a...
2018-12-14 whitequarkback.pysim: implement "sync processes", like migen...
2018-12-14 whitequarkback.pysim: allow suspending processes until a tick...
2018-12-13 whitequarkback.pysim: fix handling of process termination.
2018-12-13 whitequarkback.pysim: new simulator backend (WIP).
2018-12-13 whitequarkfhdl, back: trace and emit source locations of values.
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation.
2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level...
2018-12-12 whitequarkfhdl.ir: fix port threading code.
2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
2018-12-12 whitequarkgenlib.cdc.MultiReg: pull in from Migen.
2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInse...
2018-12-12 whitequarkInitial commit.