Assert if HiFive1 program is too large.2018-09-13T23:02:22ZTim Newsometim@sifive.comTim Newsometim@sifive.com2018-09-13T23:02:22Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=f94342b7d6e06e35e521d184b7b3570dfe512409
Put debug test stack in data instead of text2018-09-13T22:55:17ZTim Newsometim@sifive.comTim Newsometim@sifive.com2018-09-13T22:55:17Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=a96f32d19d65123a5cf4e43aa25e503530f910b9
Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"2018-09-07T01:45:14ZAndrew Watermanandrew@sifive.comAndrew Watermanandrew@sifive.com2018-09-07T01:45:14Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=9d3bc86d85d935f498065d54ead7e568f03b2824
Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)"
This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028,
under the advisement of @tommythorn in #158.
Add test case for `riscv expose_custom`.2018-08-27T20:17:51ZTim Newsometim@sifive.comTim Newsometim@sifive.com2018-08-27T20:17:51Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=4dddbc79ada7f0a836cf538676c57c8df103ccf6
Add test case for `riscv expose_custom`.
Only works against spike, where I've implemented some custom debug
registers to test against.
Neuter TriggerStoreAddressInstant
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this
test exposes another problem:
https://github.com/riscv/riscv-openocd/issues/295
For now neuter the test so the testsuite can still be useful.
Make pylint happy.2018-08-27T20:58:09ZTim Newsometim@sifive.comTim Newsometim@sifive.com2018-08-27T20:58:09Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=44fd9fdc29f2d9dddd034c9f0e9720befd1dbacb
Make pylint happy with change d1d2d953b5016b465.2018-08-24T00:08:18ZTim Newsometim@sifive.comTim Newsometim@sifive.com2018-08-24T00:08:18Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=c0aa8a601202a5de0d3334cb74f75105df627eee
Get all of the log into the final log file2018-08-24T00:04:57ZTim Newsometim@sifive.comTim Newsometim@sifive.com2018-08-24T00:04:57Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=3e972b3d78bc62914d6920c06cc9e99ef82ed492
Get all of the log into the final log file
This allows me to see the final valgrind output on OpenOCD, so I can
watch for memory leaks when using --server_cmd "valgrind
--leak-check=full openocd".
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread2018-08-23T23:52:39ZTim Newsometim@sifive.comGitHubnoreply@github.com2018-08-23T23:52:39Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=ec9250bb49897c3f2483b6aafb6158fa413a12e7
Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread
Add debug test, which checks that openocd correctly switch active thread on any hart halt.
Add debug test, which checks that openocd correctly switch active thread on any hart... 2018-08-22T15:09:33ZDmitry Ryzhovdmitry.ryzhov@cloudbear.ruDmitry Ryzhovdmitry.ryzhov@cloudbear.ru2018-08-22T15:09:33Zhttps://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff;h=d1d2d953b5016b4659ee6b57eea66b8ba9b23dc3
Add debug test, which checks that openocd correctly switch active thread on any hart halt.