Ensure there are no unnamed registers.

[riscv-tests.git] / debug / gdbserver.py

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 09938d3f1b049b4e44674be4aa901285c6fdff41..521fffbf82ec59304f64d5df9fba502a25814f47 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -396,6 +396,8 @@ class Registers(DebugTest):
             output = self.gdb.command(cmd)
             for reg in ('zero', 'ra', 'sp', 'gp', 'tp'):
                 assertIn(reg, output)
+            for line in output.splitlines():
+                assertRegexpMatches(line, r"^\S")
 
         #TODO
         # mcpuid is one of the few registers that should have the high bit set
@@ -817,7 +819,8 @@ class PrivRw(PrivTest):
         # Disable physical memory protection by allowing U mode access to all
         # memory.
         self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
-        self.gdb.p("$pmpaddr0=0x%x" % ((self.hart.ram + self.hart.ram_size) >> 2))
+        self.gdb.p("$pmpaddr0=0x%x" %
+                ((self.hart.ram + self.hart.ram_size) >> 2))
 
         # Leave the PC at _start, where the first 4 instructions should be
         # legal in any mode.