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Test debugging code with interrupts.
[riscv-tests.git] / debug / programs / entry.S
diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index a2ea955a2707ed93d1283b066d801fc46ac2d398..97b62a33f2070f4ecefa5657944a14f769264ea0 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -1,8 +1,6 @@
 #include "encoding.h"
 
-// Enough stack to store every register in case a trap handler is executed,
-// plus 33 more values.
-#define STACK_SIZE (64 * XLEN / 8)
+#define STACK_SIZE (74 * XLEN / 8)
 
 #if XLEN == 64
 # define LREG ld