Test FPRs that aren't XLEN in size.

[riscv-tests.git] / debug / targets / RISC-V / spike32.py

diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 665d7e99a56c6ae73e7364a60ef11a33f80b14f5..dfcfc0134dc26a67dedbc1ee79fd4e0d3d1c38c2 100644 (file)
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -6,13 +6,14 @@ class spike32_hart(targets.Hart):
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
     link_script_path = "spike32.lds"
 
 class spike32(targets.Target):
     harts = [spike32_hart()]
-    openocd_config_path = "spike.cfg"
+    openocd_config_path = "spike-1.cfg"
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDC")