Test FPRs that aren't XLEN in size.

[riscv-tests.git] / debug / targets / RISC-V / spike32.py

diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 809463cb697c065d365eabd6505d4f042ae07c12..dfcfc0134dc26a67dedbc1ee79fd4e0d3d1c38c2 100644 (file)
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -15,4 +15,5 @@ class spike32(targets.Target):
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDC")