Merge pull request #123 from riscv/gdb_timeout

[riscv-tests.git] / debug / targets / SiFive / Freedom / E300Sim.py

diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py
index e98c5b947448e24aaedf1f2fe2bcd233d78c96d4..f9428d077650d62c3483dcfe987dd7810ea24216 100644 (file)
--- a/debug/targets/SiFive/Freedom/E300Sim.py
+++ b/debug/targets/SiFive/Freedom/E300Sim.py
@@ -1,13 +1,17 @@
 import targets
+import testlib
 
-class E300Sim(targets.Target):
+class E300Hart(targets.Hart):
     xlen = 32
-    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
 
-    def target(self):
+class E300Sim(targets.Target):
+    timeout_sec = 6000
+    openocd_config_path = "Freedom.cfg"
+    harts = [E300Hart()]
+
+    def create(self):
         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)