Check sepc for rv64si/scall test. (#107)

[riscv-tests.git] / isa / rv64si / scall.S

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index e1c13b6464ffcef7d3f718ea0d3b93222dc249dd..0579806e9af0770cf7c04eb689e25ec29d055c9e 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -18,25 +18,54 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
+  #undef SSTATUS_SPP
+  #define SSTATUS_SPP MSTATUS_MPP
 #endif
 
   li TESTNUM, 2
+
+  # This is the expected trap code.
+  li t1, CAUSE_USER_ECALL
+
+#ifdef __MACHINE_MODE
+  # If running in M mode, use mstatus.MPP to check existence of U mode.
+  # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  csrr t1, mstatus
+  and t0, t0, t1
+  beqz t0, 1f
+
+  # If U mode doesn't exist, mcause should indicate ECALL from M mode.
+  li t1, CAUSE_MACHINE_ECALL
+#endif
+
+1:
+  li t0, SSTATUS_SPP
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  sret
+1:
+
+  li TESTNUM, 1
+do_scall:
   scall
   j fail
 
-  j pass
-
   TEST_PASSFAIL
 
+  .align 2
+  .global stvec_handler
 stvec_handler:
-  li t1, CAUSE_ECALL
   csrr t0, scause
   bne t0, t1, fail
+  la t2, do_scall
   csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
+  bne t0, t2, fail
+  j pass
 
 RVTEST_CODE_END