X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=blobdiff_plain;f=debug%2Fgdbserver.py;h=49e42e796ec807b9377165f5d8fb76e62b3fbbde;hp=09938d3f1b049b4e44674be4aa901285c6fdff41;hb=8e0f6a0b1a33d35f2248628af7333ede093341d0;hpb=3714cacfdd8f1a20f58e7e217e1d737cecdf5340

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 09938d3..49e42e7 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -817,7 +817,8 @@ class PrivRw(PrivTest):
         # Disable physical memory protection by allowing U mode access to all
         # memory.
         self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
-        self.gdb.p("$pmpaddr0=0x%x" % ((self.hart.ram + self.hart.ram_size) >> 2))
+        self.gdb.p("$pmpaddr0=0x%x" %
+                ((self.hart.ram + self.hart.ram_size) >> 2))
 
         # Leave the PC at _start, where the first 4 instructions should be
         # legal in any mode.