From: Tim Newsome <tim@sifive.com>
Date: Fri, 1 Dec 2017 22:29:11 +0000 (-0800)
Subject: Ensure there are no unnamed registers.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=b747a10a7dd789620ebcde2197581ef8bf0fda33;hp=fda427b8110777add52890641c49155f363d39ae

Ensure there are no unnamed registers.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 49e42e7..521fffb 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -396,6 +396,8 @@ class Registers(DebugTest):
             output = self.gdb.command(cmd)
             for reg in ('zero', 'ra', 'sp', 'gp', 'tp'):
                 assertIn(reg, output)
+            for line in output.splitlines():
+                assertRegexpMatches(line, r"^\S")
 
         #TODO
         # mcpuid is one of the few registers that should have the high bit set