From: Richard Xia <richardxia@richardxia.com>
Date: Fri, 27 Oct 2017 04:33:49 +0000 (-0700)
Subject: Fix rv64mi-csr for the case where U-mode is not available. (#86)
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=bb14a75c0b938dcbb308a5304ea0c3f30c3fceef

Fix rv64mi-csr for the case where U-mode is not available. (#86)
---

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 83e9cae..292e298 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -26,7 +26,23 @@ RVTEST_CODE_BEGIN
 
   # For RV64, make sure UXL encodes RV64.  (UXL does not exist for RV32.)
 #if __riscv_xlen == 64
+  # If running in M mode, read misa to check existence of U mode.
+  # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+#ifdef __MACHINE_MODE
+  csrr a0, misa
+  srli a0, a0, 'U' - 'A'
+  andi a0, a0, 1
+  beqz a0, 1f
+#endif
+  # If U mode is present, UXL should be 2 (XLEN = 64-bit)
   TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
+#ifdef __MACHINE_MODE
+  j 2f
+1:
+  # If U mode is not present, UXL should be 0
+  TEST_CASE(14, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
+2:
+#endif
 #endif
 
   csrwi sscratch, 3