From: Christopher Celio <celio@eecs.berkeley.edu>
Date: Wed, 10 Sep 2014 21:17:01 +0000 (-0700)
Subject: Enable interrupts in bmarks
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=dbde501592ce20c536cbc97e99d03f54f3e30294

Enable interrupts in bmarks
---

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 82cad93..e35608e 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -44,21 +44,20 @@ _start:
   li  x30,0
   li  x31,0
 
+  # initialize status, enable fp, accelerator, interrupts
+  li a0, SR_S | SR_PEI | SR_EF | SR_EA
+  csrw status, a0
+
 #ifdef __riscv64
   li a0, SR_U64 | SR_S64
   csrs status, a0
 #endif
-  csrc status, SR_PS
-
-  # enable fp and accelerator
-  li a0, SR_EF | SR_EA
-  csrs status, a0
 
   csrr t0, status
   and t1, t0, SR_EA
   sw t1, have_vec, t2
 
-  ## if that didn't stick, we don't have an FPU, so don't initialize it
+  ## if that didn't stick, we don't have a FPU, so don't initialize it
   and t1, t0, SR_EF
   beqz t1, 1f