From: Richard Xia <rxia@sifive.com>
Date: Mon, 7 Aug 2017 23:57:14 +0000 (-0700)
Subject: rv64[ms]i-csr: Only emit F instructions when compiled for F.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=de8fd3d35667d84a6de3aa5cd91d3da3b437b00e

rv64[ms]i-csr: Only emit F instructions when compiled for F.
---

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 0576678..83e9cae 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -47,10 +47,15 @@ RVTEST_CODE_BEGIN
   # If so, make sure FP stores have no effect when mstatus.FS is off.
   li a1, MSTATUS_FS
   csrs mstatus, a1
+#ifdef __riscv_flen
   fmv.s.x f0, x0
   csrc mstatus, a1
   la a1, fsw_data
   TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
+#else
+  # Fail if this test is compiled without F but executed on a core with F.
+  TEST_CASE(10, zero, 1)
+#endif
 1:
 
   # Figure out if 'U' is set in misa
@@ -58,7 +63,7 @@ RVTEST_CODE_BEGIN
   srli a0, a0, 20 # a0 = a0 >> 20
   andi a0, a0, 1  # a0 = a0 & 1
   beqz a0, finish # if no user mode, skip the rest of these checks
-#endif
+#endif /* __MACHINE_MODE */
 
   # jump to user land
   li t0, SSTATUS_SPP