From: Tim Newsome <tim@sifive.com>
Date: Wed, 20 Sep 2017 00:10:36 +0000 (-0700)
Subject: Allow multiple reset vectors.
X-Git-Url: https://git.libre-soc.org/?p=riscv-tests.git;a=commitdiff_plain;h=fcd0e956339560021e2a16a143697b8123f227d6

Allow multiple reset vectors.

Some boards have jumpers that control the reset vector, and forcing them
one way or another is more annoying than dealing with it in software.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index d0ad46e..135dab8 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -217,7 +217,7 @@ class InstantHaltTest(GdbTest):
             self.gdb.thread(t)
             pcs.append(self.gdb.p("$pc"))
         for pc in pcs:
-            assertEqual(self.hart.reset_vector, pc)
+            assertIn(pc, self.hart.reset_vectors)
         # mcycle and minstret have no defined reset value.
         mstatus = self.gdb.p("$mstatus")
         assertEqual(mstatus & (MSTATUS_MIE | MSTATUS_MPRV |
diff --git a/debug/targets.py b/debug/targets.py
index d661d14..d09b576 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -34,6 +34,11 @@ class Hart(object):
     # Defaults to target-<index>
     name = None
 
+    # When reset, the PC must be at one of the values listed here.
+    # This is a list because on some boards the reset vector depends on
+    # jumpers.
+    reset_vectors = []
+
     def extensionSupported(self, letter):
         # target.misa is set by testlib.ExamineTarget
         if self.misa:
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 665d7e9..bcb5892 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -6,7 +6,7 @@ class spike32_hart(targets.Hart):
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
     link_script_path = "spike32.lds"
 
 class spike32(targets.Target):
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 6e3da89..9c37f87 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -6,7 +6,7 @@ class spike64_hart(targets.Hart):
     ram = 0x1212340000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
-    reset_vector = 0x1000
+    reset_vectors = [0x1000]
     link_script_path = "spike64.lds"
 
 class spike64(targets.Target):