From a0259333dcd4bbba2dbfaeb7bfb9145c56cf96ca Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 18 Sep 2017 11:31:08 -0700 Subject: [PATCH] Add interrupts to MulticoreRunHaltStepiTest. Just to hammer on anything at once, and hopefully catch weird interactions if they exist. --- debug/gdbserver.py | 9 ++++++++- debug/programs/entry.S | 2 +- debug/programs/multicore.c | 31 +++++++++++++++++++------------ debug/testlib.py | 3 +-- 4 files changed, 29 insertions(+), 16 deletions(-) diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 9fedbca..d0ad46e 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -529,14 +529,21 @@ class MulticoreRunHaltStepiTest(GdbTest): def test(self): previous_hart_count = [0 for h in self.target.harts] + previous_interrupt_count = [0 for h in self.target.harts] for _ in range(10): self.gdb.c(wait=False) - time.sleep(1) + time.sleep(2) self.gdb.interrupt() + self.gdb.p("$mie") + self.gdb.p("$mip") + self.gdb.p("$mstatus") + self.gdb.p("$priv") self.gdb.p("buf", fmt="") hart_count = self.gdb.p("hart_count") + interrupt_count = self.gdb.p("interrupt_count") for i, h in enumerate(self.target.harts): assertGreater(hart_count[i], previous_hart_count[i]) + assertGreater(interrupt_count[i], previous_interrupt_count[i]) self.gdb.select_hart(h) pc = self.gdb.p("$pc") self.gdb.stepi() diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 97b62a3..35c233e 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -1,6 +1,6 @@ #include "encoding.h" -#define STACK_SIZE (74 * XLEN / 8) +#define STACK_SIZE (90 * XLEN / 8) #if XLEN == 64 # define LREG ld diff --git a/debug/programs/multicore.c b/debug/programs/multicore.c index d7dd845..272baea 100644 --- a/debug/programs/multicore.c +++ b/debug/programs/multicore.c @@ -1,5 +1,7 @@ #include +#include "init.h" + typedef struct { int counter; } atomic_t; @@ -15,14 +17,6 @@ static inline int atomic_xchg(atomic_t *v, int n) return c; } -#define csr_read(csr) \ -({ \ - register unsigned long __v; \ - __asm__ __volatile__ ("csrr %0, " #csr \ - : "=r" (__v)); \ - __v; \ -}) - static inline void mb(void) { __asm__ __volatile__ ("fence"); @@ -44,19 +38,31 @@ void put_lock(atomic_t *lock) static atomic_t buf_lock = { .counter = 0 }; static char buf[32]; static int buf_initialized; -static unsigned hart_count[2]; +static unsigned hart_count[NHARTS]; +static unsigned interrupt_count[NHARTS]; -static const char case_bit = 'a' - 'A'; -volatile int initialized; +static unsigned delta = 0x100; +void *increment_count(unsigned hartid, unsigned mcause, void *mepc, void *sp) +{ + interrupt_count[hartid]++; + MTIMECMP[hartid] = MTIME + delta; + return mepc; +} int main() { uint32_t hartid = csr_read(mhartid); hart_count[hartid] = 0; + interrupt_count[hartid] = 0; + + set_trap_handler(increment_count); + // Despite being memory-mapped, there appears to be one mtimecmp + // register per hart. The spec does not address this. + MTIMECMP[hartid] = MTIME + delta; + enable_timer_interrupts(); while (1) { get_lock(&buf_lock); - hart_count[hartid]++; if (!buf_initialized) { for (unsigned i = 0; i < sizeof(buf); i++) { @@ -77,5 +83,6 @@ int main() buf[i] = 'a' + ((i + hartid + hart_count[hartid]) % 26); } put_lock(&buf_lock); + hart_count[hartid]++; } } diff --git a/debug/testlib.py b/debug/testlib.py index 3eeace9..996c188 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -540,8 +540,7 @@ def header(title, dash='-', length=78): def print_log(path): header(path) - lines = open(path, "r").readlines() - for l in lines: + for l in open(path, "r"): sys.stdout.write(l) print -- 2.30.2