interface MUX#(numeric type ionum);
interface MUX_config#(ionum) mux_config;
- interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
endinterface
// (*synthesize*)
- module mkmux(MUX#(ionum_));
- Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg <-replicateM(mkConfigReg(0));
-
- AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
+ module mkmux#(Bit#(TMul#(ionum_, 2)) defvalue)(MUX#(ionum_));
let ionum=valueOf(ionum_);
+ Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg ;
+ for(Integer i=0;i<ionum;i=i+ 1)
+ muxer_reg[i]<-mkConfigReg(defvalue[i*2+ 1:i*2]);
+
+ AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
rule rl_wr_respond;
// Get the wr request
//aw is write address, w is write data