From a53da17efe5132fbca2641edae167f1348497339 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 27 Jul 2018 10:09:15 +0100 Subject: [PATCH] format and comment quart --- src/peripherals/uart/quart.bsv | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/src/peripherals/uart/quart.bsv b/src/peripherals/uart/quart.bsv index 392dcdd..f8aee3d 100644 --- a/src/peripherals/uart/quart.bsv +++ b/src/peripherals/uart/quart.bsv @@ -56,21 +56,17 @@ package quart; (QUART_AXI4_Lite_Ifc); Uart16550_AXI4_Lite_Ifc uart <- mkUart16550(core_clock, core_reset); - //uart.pin_dsr_sync <= in; - //uart.pin_ri_sync <= in; - //uart.pin_dcd_sync <= in; + + // ok set up CDC and dsr to 1, and Ring to 0. and otherwise ignore them rule rl_put; - Bit#(1) v1 = 1; - Bit#(1) v0 = 1; - uart.coe_rs232.dsr_in.put(1); - - uart.coe_rs232.dcd_in.put(1); - uart.coe_rs232.ri_in.put(0); + uart.coe_rs232.dsr_in.put(1); + uart.coe_rs232.dcd_in.put(1); + uart.coe_rs232.ri_in.put(0); endrule - + // deliberately drop (ignore) this value rule rl_get; - let temp2 <- uart.coe_rs232.dtr_out.get; + let temp2 <- uart.coe_rs232.dtr_out.get; endrule interface out = interface QUART_out -- 2.30.2