From d48d22ca2b5e297e1b727dc5d626521ffc70bef8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 10:05:36 +0100 Subject: [PATCH] add test and convert jtag to get/put --- src/peripherals/jtagdtm/Makefile | 45 +++++++++++++++++++ src/peripherals/jtagdtm/jtagdtm.bsv | 44 +++++++++++++----- .../jtagdtm/test/instance_defines.bsv | 24 ++++++++++ 3 files changed, 102 insertions(+), 11 deletions(-) create mode 100644 src/peripherals/jtagdtm/Makefile create mode 100644 src/peripherals/jtagdtm/test/instance_defines.bsv diff --git a/src/peripherals/jtagdtm/Makefile b/src/peripherals/jtagdtm/Makefile new file mode 100644 index 0000000..4991d96 --- /dev/null +++ b/src/peripherals/jtagdtm/Makefile @@ -0,0 +1,45 @@ +### Makefile for the cclass project + +TOP_MODULE:=mkjtagdtm +TOP_FILE:=jtagdtm.bsv +TOP_DIR:=./ +WORKING_DIR := $(shell pwd) + +BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/ +BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4 +BSVINCDIR:= $(BSVINCDIR):../../lib +BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite +BSVINCDIR:= $(BSVINCDIR):./test + +default: gen_verilog + +check-blue: + @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; + +###### Setting the variables for bluespec compile #$############################ +BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules +BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires +VERILOGDIR:=./verilog/ +BSVBUILDDIR:=./bsv_build/ +BSVOUTDIR:=./bin +################################################################################ + +########## BSIM COMPILE, LINK AND SIMULATE TARGETS ########################## +.PHONY: check-restore +check-restore: + @if [ "$(define_macros)" != "$(old_define_macros)" ]; then make clean ; fi; + +.PHONY: gen_verilog +gen_verilog: check-restore check-blue + @echo Compiling mkTbSoc in Verilog for simulations ... + @mkdir -p $(BSVBUILDDIR); + @mkdir -p $(VERILOGDIR); + bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log + @echo Compilation finished + +############################################################################# + +.PHONY: clean +clean: + rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl* + rm -rf verilog obj_dir bsv_src diff --git a/src/peripherals/jtagdtm/jtagdtm.bsv b/src/peripherals/jtagdtm/jtagdtm.bsv index aea5b37..cf5ae69 100644 --- a/src/peripherals/jtagdtm/jtagdtm.bsv +++ b/src/peripherals/jtagdtm/jtagdtm.bsv @@ -15,13 +15,14 @@ package jtagdtm; /*====== Package imports ======= */ import Clocks::*; import ConcatReg::*; + import GetPut::*; import FIFO::*; import FIFOF::*; import SpecialFIFOs::*; import DReg::*; /*======= Project imports ===== */ `include "jtagdefines.bsv" - import defined_types::*; + //import defined_types::*; /*============================== */ interface Ifc_jtagdtm; @@ -69,15 +70,18 @@ interface Ifc_jtagdtm; method Bit#(1) scan_shift_en; /*======== JTAG input pins ===== */ (*always_enabled,always_ready*) - method Action tms_i(Bit#(1) tms); + interface Put#(Bit#(1)) tms; (*always_enabled,always_ready*) - method Action tdi_i(Bit#(1) tdi); + interface Put#(Bit#(1)) tdi; /*==== inputs from Sub-modules === */ method Action debug_tdi_i(Bit#(1) debug_tdi); /*======= JTAG Output Pins ====== */ (*always_enabled,always_ready*) - method Bit#(1) tdo; + interface Get#(Bit#(1)) tdo; method Bit#(1) tdo_oe; + (*always_enabled,always_ready*) + interface Get#(Bit#(1)) tck; + /*======== TAP States ============= */ method Bit#(1) shift_dr; method Bit#(1) pause_dr; @@ -514,12 +518,19 @@ typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4 scan_out_5_sr<=scan_out_5; endmethod /*======== JTAG input pins ===== */ - method Action tms_i(Bit#(1) tms); - wr_tms<=tms; - endmethod - method Action tdi_i(Bit#(1) tdi); - wr_tdi<=tdi; - endmethod + + interface tms = interface Put + method Action put(Bit#(1) in); + wr_tms<=in; + endmethod + endinterface; + + interface tdi = interface Put + method Action put(Bit#(1) in); + wr_tdi<=in; + endmethod + endinterface; + /*============================= */ method Action debug_tdi_i(Bit#(1) debug_tdi); wr_debug_tdi<=debug_tdi; @@ -552,7 +563,18 @@ typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4 method bscan_in = bs_sr; method scan_shift_en = wr_scan_shift_en[1]; /*======= JTAG Output Pins ====== */ - method tdo = crossed_output_tdo; + interface tck = interface Get + method ActionValue#(Bit#(1)) get; + return 'b1; //#def_clk; + endmethod + endinterface; + + interface tdo = interface Get + method ActionValue#(Bit#(1)) get; + return crossed_output_tdo; + endmethod + endinterface; + method debug_tdo = wr_tdi; method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0; method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull); diff --git a/src/peripherals/jtagdtm/test/instance_defines.bsv b/src/peripherals/jtagdtm/test/instance_defines.bsv new file mode 100644 index 0000000..38780f5 --- /dev/null +++ b/src/peripherals/jtagdtm/test/instance_defines.bsv @@ -0,0 +1,24 @@ +`define ADDR 32 +`define PADDR 32 +`define DATA 64 +`define Reg_width 64 +`define USERSPACE 0 + +// TODO: work out if these are needed +`define PWM_AXI4Lite +`define PRFDEPTH 6 +`define VADDR 39 +`define DCACHE_BLOCK_SIZE 4 +`define DCACHE_WORD_SIZE 8 +`define PERFMONITORS 64 +`define DCACHE_WAYS 4 +`define DCACHE_TAG_BITS 20 // tag_bits = 52 +`define PLIC + `define PLICBase 'h0c000000 + `define PLICEnd 'h10000000 +`define INTERRUPT_PINS 64 + +`define BAUD_RATE 130 +`ifdef simulate + `define BAUD_RATE 5 //130 // +`endif -- 2.30.2