diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIO.scala

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index d4cd24e07d58541f1b6a08fa88cdb907072485e9..f598dbb00c0dac677202f160b8638e1dd9f85ee1 100644 (file)
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.util.SynchronizerShiftReg
@@ -87,7 +88,7 @@ trait HasGPIOBundleContents extends Bundle {
   val port = new GPIOPortIO(params)
 }
 
-trait HasGPIOModuleContents extends Module with HasRegMap {
+trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
   val io: HasGPIOBundleContents
   val params: GPIOParams
   val c = params