diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIO.scala

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index e7a48299d132df91965224608386f61812b810f4..f598dbb00c0dac677202f160b8638e1dd9f85ee1 100644 (file)
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -2,8 +2,10 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
@@ -82,11 +84,11 @@ class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
 // It would be better if the IOF were here and
 // we could do the pinmux inside.
 trait HasGPIOBundleContents extends Bundle {
-  val params: GPIOParams
+  def params: GPIOParams
   val port = new GPIOPortIO(params)
 }
 
-trait HasGPIOModuleContents extends Module with HasRegMap {
+trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
   val io: HasGPIOBundleContents
   val params: GPIOParams
   val c = params
@@ -106,7 +108,7 @@ trait HasGPIOModuleContents extends Module with HasRegMap {
   // Synchronize Input to get valueReg
   val inVal = Wire(UInt(0, width=c.width))
   inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
-  val inSyncReg  = ShiftRegister(inVal, 3)
+  val inSyncReg  = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
   val valueReg   = Reg(init = UInt(0, c.width), next = inSyncReg)
 
   // Interrupt Configuration