package sifive.blocks.devices.gpio
import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
-trait HasPeripheryGPIO extends HasTopLevelNetworks {
+trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
val gpioParams = p(PeripheryGPIOKey)
- val gpio = gpioParams map {params =>
- val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
- gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := gpio.intnode
+ val gpios = gpioParams map { params =>
+ val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
+ gpio.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := gpio.intnode
gpio
}
}
-trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripheryGPIO
- val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
+trait HasPeripheryGPIOBundle {
+ val gpio: HeterogeneousBag[GPIOPortIO]
}
-trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
+trait HasPeripheryGPIOModuleImp extends LazyModuleImp with HasPeripheryGPIOBundle {
val outer: HasPeripheryGPIO
- val io: HasPeripheryGPIOBundle
- (io.gpio zip outer.gpio) foreach { case (io, device) =>
+ val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
+
+ (gpio zip outer.gpios) foreach { case (io, device) =>
io <> device.module.io.port
}
}