projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
diplomacy: update to new API (#40)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
i2c
/
I2C.scala
diff --git
a/src/main/scala/devices/i2c/I2C.scala
b/src/main/scala/devices/i2c/I2C.scala
index 147a739b6041c01f361eb208bd6ce37345fedf07..aecf2dca476cde9bb5bfb94adbb650ed988b0959 100644
(file)
--- a/
src/main/scala/devices/i2c/I2C.scala
+++ b/
src/main/scala/devices/i2c/I2C.scala
@@
-42,6
+42,7
@@
package sifive.blocks.devices.i2c
import Chisel._
package sifive.blocks.devices.i2c
import Chisel._
+import chisel3.experimental.MultiIOModule
import freechips.rocketchip.config._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.config._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@@
-64,7
+65,7
@@
trait HasI2CBundleContents extends Bundle {
val port = new I2CPort
}
val port = new I2CPort
}
-trait HasI2CModuleContents extends Module with HasRegMap {
+trait HasI2CModuleContents extends M
ultiIOM
odule with HasRegMap {
val io: HasI2CBundleContents
val params: I2CParams
val io: HasI2CBundleContents
val params: I2CParams