diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / mockaon / MockAONPeriphery.scala

diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index 3f0d3268b3485c7c0deb80e9ac9869b9f14ddb9b..8de7ad9ba1d20a85d870241b3d40c7ebe84097d2 100644 (file)
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -3,10 +3,11 @@ package sifive.blocks.devices.mockaon
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.devices.debug.HasPeripheryDebug
 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
 import freechips.rocketchip.util.ResetCatchAndSync
 
@@ -31,7 +32,7 @@ trait HasPeripheryMockAONBundle {
   }
 }
 
-trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle {
+trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
   val outer: HasPeripheryMockAON
   val aon = IO(new MockAONWrapperBundle)
 
@@ -43,7 +44,7 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
   outer.aon.module.reset := Bool(true)
 
   // Synchronize the external toggle into the clint
-  val rtc_sync = ShiftRegister(outer.aon.module.io.rtc.asUInt.toBool, 3)
+  val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
   val rtc_last = Reg(init = Bool(false), next=rtc_sync)
   val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))