diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / pwm / PWM.scala

diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index 044d1bd589bd0c06d800c9e723bc2aa46561e0ed..638100496dabfb564b597a335d05e57c68aef041 100644 (file)
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import Chisel.ImplicitConversions._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.regmapper._
@@ -44,11 +45,11 @@ case class PWMParams(
   cmpWidth: Int = 16)
 
 trait HasPWMBundleContents extends Bundle {
-  val params: PWMParams
+  def params: PWMParams
   val gpio = Vec(params.ncmp, Bool()).asOutput
 }
 
-trait HasPWMModuleContents extends Module with HasRegMap {
+trait HasPWMModuleContents extends MultiIOModule with HasRegMap {
   val io: HasPWMBundleContents
   val params: PWMParams