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diplomacy: update to new API (#40)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
pwm
/
PWM.scala
diff --git
a/src/main/scala/devices/pwm/PWM.scala
b/src/main/scala/devices/pwm/PWM.scala
index 3d35d81cf49fcbf5a8a64bc5a07e28a9204f2611..638100496dabfb564b597a335d05e57c68aef041 100644
(file)
--- a/
src/main/scala/devices/pwm/PWM.scala
+++ b/
src/main/scala/devices/pwm/PWM.scala
@@
-2,6
+2,7
@@
package sifive.blocks.devices.pwm
import Chisel._
package sifive.blocks.devices.pwm
import Chisel._
+import chisel3.experimental.MultiIOModule
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
@@
-48,7
+49,7
@@
trait HasPWMBundleContents extends Bundle {
val gpio = Vec(params.ncmp, Bool()).asOutput
}
val gpio = Vec(params.ncmp, Bool()).asOutput
}
-trait HasPWMModuleContents extends Module with HasRegMap {
+trait HasPWMModuleContents extends M
ultiIOM
odule with HasRegMap {
val io: HasPWMBundleContents
val params: PWMParams
val io: HasPWMBundleContents
val params: PWMParams