package sifive.blocks.devices.pwm
import Chisel._
+import chisel3.experimental.MultiIOModule
import Chisel.ImplicitConversions._
-import config.Parameters
-import regmapper._
-import uncore.tilelink2._
-import util._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface
cmpWidth: Int = 16)
trait HasPWMBundleContents extends Bundle {
- val params: PWMParams
+ def params: PWMParams
val gpio = Vec(params.ncmp, Bool()).asOutput
}
-trait HasPWMModuleContents extends Module with HasRegMap {
+trait HasPWMModuleContents extends MultiIOModule with HasRegMap {
val io: HasPWMBundleContents
val params: PWMParams
}
class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
- extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = w)(
+ extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
new TLRegBundle(c, _) with HasPWMBundleContents)(
new TLRegModule(c, _, _) with HasPWMModuleContents)