diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / pwm / PWM.scala

diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index c649e7e376eec6cf7e48737a50291bf123ddb69a..638100496dabfb564b597a335d05e57c68aef041 100644 (file)
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -2,18 +2,17 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import Chisel.ImplicitConversions._
-import config._
-import regmapper._
-import rocketchip.PeripheryBusConfig
-import uncore.tilelink2._
-import util._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
 import sifive.blocks.util.GenericTimer
 
 // Core PWM Functionality  & Register Interface
 
-class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) extends GenericTimer {
+class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16) extends GenericTimer {
   protected def countWidth = ((1 << scaleWidth) - 1) + cmpWidth
   protected lazy val countAlways = RegEnable(io.regs.cfg.write.bits(12), Bool(false), io.regs.cfg.write.valid && unlocked)
   protected lazy val feed = count.carryOut(scale + UInt(cmpWidth))
@@ -38,45 +37,31 @@ class PWM(val ncmp: Int = 4, val cmpWidth: Int = 16)(implicit p: Parameters) ext
   countEn := countAlways || oneShot
 }
 
-case class PWMConfig(
+case class PWMParams(
   address: BigInt,
   size: Int = 0x1000,
   regBytes: Int = 4,
   ncmp: Int = 4,
   cmpWidth: Int = 16)
-{
-  val bc = new PWMBundleConfig(ncmp)
-}
-
-case class PWMBundleConfig(
-  ncmp: Int)
-{
-  def union(that: PWMBundleConfig): PWMBundleConfig =
-    PWMBundleConfig(scala.math.max(ncmp, that.ncmp))
-}
-
-trait HasPWMParameters {
-  implicit val p: Parameters
-  val params: PWMConfig
-  val c = params
-}
 
-trait PWMBundle extends Bundle with HasPWMParameters {
-  val gpio = Vec(c.ncmp, Bool()).asOutput
+trait HasPWMBundleContents extends Bundle {
+  def params: PWMParams
+  val gpio = Vec(params.ncmp, Bool()).asOutput
 }
 
-trait PWMModule extends Module with HasRegMap with HasPWMParameters {
-  val io: PWMBundle
+trait HasPWMModuleContents extends MultiIOModule with HasRegMap {
+  val io: HasPWMBundleContents
+  val params: PWMParams
 
-  val pwm = Module(new PWM(c.ncmp, c.cmpWidth))
+  val pwm = Module(new PWM(params.ncmp, params.cmpWidth))
 
   interrupts := pwm.io.ip
   io.gpio := pwm.io.gpio
 
-  regmap((GenericTimer.timerRegMap(pwm, 0, c.regBytes)):_*)
+  regmap((GenericTimer.timerRegMap(pwm, 0, params.regBytes)):_*)
 }
 
-class TLPWM(c: PWMConfig)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = p(PeripheryBusConfig).beatBytes)(
-  new TLRegBundle(c, _)    with PWMBundle)(
-  new TLRegModule(c, _, _) with PWMModule)
+class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
+  extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
+  new TLRegBundle(c, _)    with HasPWMBundleContents)(
+  new TLRegModule(c, _, _) with HasPWMModuleContents)