device pins: Create classes that can be something other than a Pin subclass

[sifive-blocks.git] / src / main / scala / devices / pwm / PWMPeriphery.scala

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 63bbfabccc48a6f7e0a9dd256193a0fe378a93fe..94f65dd760e8c5d75537fc380140492a689526d8 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -3,22 +3,31 @@ package sifive.blocks.devices.pwm
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
-import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
+import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
+class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
 
   val pwm: Vec[T] = Vec(c.ncmp, pingen())
 
-  def fromPWMPort(port: PWMPortIO) {
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+}
+
+
+class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends PWMSignals[T](pingen, c) {
+
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+
+  def fromPort(port: PWMPortIO) {
     (pwm zip port.port)  foreach {case (pin, port) =>
       pin.outputPin(port)
     }
@@ -27,26 +36,26 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
   val pwmParams = p(PeripheryPWMKey)
   val pwms = pwmParams map { params =>
-    val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
-    pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := pwm.intnode
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+    pwm.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := pwm.intnode
     pwm
   }
 }
 
 trait HasPeripheryPWMBundle {
-  val pwms: HeterogeneousBag[PWMPortIO]
+  val pwm: HeterogeneousBag[PWMPortIO]
 
 }
 
 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
-  val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+  val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
 
-  (pwms zip outer.pwms) foreach { case (io, device) =>
+  (pwm zip outer.pwms) foreach { case (io, device) =>
     io.port := device.module.io.gpio
   }
 }