devices: include DTS meta-data

[sifive-blocks.git] / src / main / scala / devices / spi / TLSPI.scala

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index c3a137ce2ac22262f8333075f4fb49a6e8d67fcf..b20b5246c3e5a813ee51e67f16d0712a56c6bede 100644 (file)
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -109,8 +109,9 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
 
 abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
-  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = w)
-  val intnode = IntSourceNode(1)
+  val device = new SimpleDevice("spi", Seq("sifive,spi0"))
+  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
+  val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 }
 
 class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {