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diplomacy: update to new API (#40)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
TLSPI.scala
diff --git
a/src/main/scala/devices/spi/TLSPI.scala
b/src/main/scala/devices/spi/TLSPI.scala
index 0af8e35150ba077fc573f33074f39a699e0fcd5a..ea28f8936be87b1d9dd9f5e169b088bdff2f78d6 100644
(file)
--- a/
src/main/scala/devices/spi/TLSPI.scala
+++ b/
src/main/scala/devices/spi/TLSPI.scala
@@
-47,15
+47,12
@@
case class SPIParams(
require(sampleDelay >= 0)
}
require(sampleDelay >= 0)
}
-class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle
-
-class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
+class SPITopModule(c: SPIParamsBase, outer: TLSPIBase)
extends LazyModuleImp(outer) {
extends LazyModuleImp(outer) {
- val io = new Bundle {
+ val io =
IO(
new Bundle {
val port = new SPIPortIO(c)
val port = new SPIPortIO(c)
- val tl = bundle
- }
+ })
val ctrl = Reg(init = SPIControl.init(c))
val ctrl = Reg(init = SPIControl.init(c))
@@
-72,7
+69,8
@@
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
val ip = fifo.io.ip
val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
val ip = fifo.io.ip
- io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
+ val (io_int, _) = outer.intnode.out(0)
+ io_int(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
protected val regmapBase = Seq(
SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
protected val regmapBase = Seq(
SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
@@
-115,7
+113,7
@@
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) exten
}
class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
}
class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
- lazy val module = new SPITopModule(c,
new SPITopBundle(intnode.bundleOut, rnode.bundleIn),
this) {
+ lazy val module = new SPITopModule(c, this) {
mac.io.link <> fifo.io.link
rnode.regmap(regmapBase:_*)
}
mac.io.link <> fifo.io.link
rnode.regmap(regmapBase:_*)
}