diplomacy: update to new API (#40)

[sifive-blocks.git] / src / main / scala / devices / uart / UART.scala

diff --git a/src/main/scala/devices/uart/UART.scala b/src/main/scala/devices/uart/UART.scala
index 58722e112eaafe5edebaf9b121b6162b2edd853b..449f897819a57427a8a8e978569df70745bebe2b 100644 (file)
--- a/src/main/scala/devices/uart/UART.scala
+++ b/src/main/scala/devices/uart/UART.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.uart
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
@@ -69,10 +70,14 @@ class UARTTx(c: UARTParams)(implicit p: Parameters) extends UARTModule(c)(p) {
   val out = Reg(init = Bits(1, 1))
   io.out := out
 
+  val plusarg_tx = PlusArg("uart_tx", 1, "Enable/disable the TX to speed up simulation").orR
+
   val busy = (counter =/= UInt(0))
   io.in.ready := io.en && !busy
   when (io.in.fire()) {
-    printf("%c", io.in.bits)
+    printf("UART TX (%x): %c\n", io.in.bits, io.in.bits)
+  }
+  when (io.in.fire() && plusarg_tx) {
     shifter := Cat(io.in.bits, Bits(0, 1))
     counter := Mux1H((0 until uartStopBits).map(i =>
       (io.nstop === UInt(i)) -> UInt(n + i + 1)))
@@ -194,7 +199,7 @@ class UARTInterrupts extends Bundle {
   val txwm = Bool()
 }
 
-trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
+trait HasUARTTopModuleContents extends MultiIOModule with HasUARTParameters with HasRegMap {
   val io: HasUARTTopBundleContents
   implicit val p: Parameters
   def params: UARTParams