pinctrl: Create extendable Signal classes

[sifive-blocks.git] / src / main / scala / devices / uart / UARTPins.scala

diff --git a/src/main/scala/devices/uart/UARTPins.scala b/src/main/scala/devices/uart/UARTPins.scala
index a5885a29364f789add85c552465178d303a86419..e04fdf3d2514ed362313a09ac16ec9fe5641eea3 100644 (file)
--- a/src/main/scala/devices/uart/UARTPins.scala
+++ b/src/main/scala/devices/uart/UARTPins.scala
@@ -9,7 +9,6 @@ import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInter
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
 
-
 class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
   val rxd = pingen()
   val txd = pingen()
@@ -18,14 +17,13 @@ class UARTSignals[T <: Data] (pingen: () => T) extends Bundle {
     this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
 }
 
-class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen, c) {
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+class UARTPins[T <: Pin] (pingen: () => T) extends UARTSignals[T](pingen)
 
-  def fromPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+object UARTPinsFromPort {
+  def apply[T <: Pin](pins: UARTSignals[T], uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
     withClockAndReset(clock, reset) {
-      txd.outputPin(uart.txd)
-      val rxd_t = rxd.inputPin()
+      pins.txd.outputPin(uart.txd)
+      val rxd_t = pins.rxd.inputPin()
       uart.rxd := SyncResetSynchronizerShiftReg(rxd_t, syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
     }
   }