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vc707mig: use an external ibuf
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707mig
/
XilinxVC707MIG.scala
diff --git
a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 58d14f4de44c3a28234abf15d54ebb222a04a7d5..f6ae153107a4ff9558056f54c3703004baab7643 100644
(file)
--- a/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@
-77,9
+77,8
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
- //differential system clock
- blackbox.io.sys_clk_n := io.port.sys_clk_n
- blackbox.io.sys_clk_p := io.port.sys_clk_p
+ //NO_BUFFER clock
+ blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
//user interface signals
val axi_async = axi4.bundleIn(0)