axi4: switch to new pipelined converters

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index f657459637f903ed4c86fb0addafba70b0563815..2e376d0fc9d7a0db3cf499ee1586a253a48dbf8b 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -26,9 +26,31 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   val intnode = IntOutputNode()
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
-  axi_to_pcie_x1.slave   := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
-  axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
-  master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+
+  axi_to_pcie_x1.slave :=
+    AXI4Buffer()(
+    AXI4UserYanker()(
+    AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
+    AXI4IdIndexer(idBits=4)(
+    TLToAXI4(beatBytes=8)(
+    slave)))))
+
+  axi_to_pcie_x1.control :=
+    AXI4Buffer()(
+    AXI4UserYanker()(
+    AXI4Fragmenter()(
+    AXI4IdIndexer(idBits=0)(
+    TLToAXI4(beatBytes=4)(
+    control)))))
+
+  master :=
+    TLWidthWidget(8)(
+    AXI4ToTL()(
+    AXI4UserYanker(capMaxFlight=Some(8))(
+    AXI4Fragmenter()(
+    AXI4IdIndexer(idBits=0)(
+    axi_to_pcie_x1.master)))))
+
   intnode := axi_to_pcie_x1.intnode
 
   lazy val module = new LazyModuleImp(this) {