package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.coreplex.CacheBlockBytes
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
- val slave = TLInputNode()
- val control = TLInputNode()
- val master = TLOutputNode()
+ val slave = TLAsyncInputNode()
+ val control = TLAsyncInputNode()
+ val master = TLAsyncOutputNode()
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
axi_to_pcie_x1.slave :=
AXI4Buffer()(
AXI4UserYanker()(
- AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
+ AXI4Deinterleaver(p(CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
- TLToAXI4(beatBytes=8)(
- slave)))))
+ TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
+ TLAsyncCrossingSink()(
+ slave))))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
- AXI4UserYanker()(
- AXI4Fragmenter()(
- AXI4IdIndexer(idBits=0)(
+ AXI4UserYanker(capMaxFlight = Some(2))(
TLToAXI4(beatBytes=4)(
+ TLFragmenter(4, p(CacheBlockBytes))(
+ TLAsyncCrossingSink()(
control)))))
master :=
+ TLAsyncCrossingSource()(
TLWidthWidget(8)(
AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()(
- AXI4IdIndexer(idBits=0)(
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode