xilinx ip: adjust to new diplomacy API

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1Periphery.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 494d787a791504c4f3b2e9a941b74e677d7134b0..4a64766dbbb719e23e12abb8f515ebf4ebc4f1d6 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -3,10 +3,10 @@ package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
 import diplomacy.LazyModule
-import rocketchip.{L2Crossbar,L2CrossbarModule,L2CrossbarBundle}
+import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
 import uncore.tilelink2.TLWidthWidget
 
-trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
+trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
   l2.node := xilinxvc707pcie.master
@@ -15,11 +15,11 @@ trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
   intBus.intnode := xilinxvc707pcie.intnode
 }
 
-trait PeripheryXilinxVC707PCIeX1Bundle extends L2CrossbarBundle {
+trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
   val xilinxvc707pcie = new XilinxVC707PCIeX1IO
 }
 
-trait PeripheryXilinxVC707PCIeX1Module extends L2CrossbarModule {
+trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
   val outer: PeripheryXilinxVC707PCIeX1
   val io: PeripheryXilinxVC707PCIeX1Bundle