uart: make it easy to simulate large text printouts (#33)

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1Periphery.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 4a64766dbbb719e23e12abb8f515ebf4ebc4f1d6..b55ec4ddcf1d47d3e181620d5379ee2d7136bc62 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -2,26 +2,32 @@
 package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
-import uncore.tilelink2.TLWidthWidget
-
-trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
+import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 
+trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  l2.node := xilinxvc707pcie.master
-  xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  intBus.intnode := xilinxvc707pcie.intnode
+
+  sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
+  xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
+  xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
+  ibus.fromAsync := xilinxvc707pcie.intnode
 }
 
-trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
-  val xilinxvc707pcie = new XilinxVC707PCIeX1IO
+trait HasSystemXilinxVC707PCIeX1Bundle {
+  val xilinxvc707pcie: XilinxVC707PCIeX1IO
+  def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
+    pads <> xilinxvc707pcie
+  }
 }
 
-trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
-  val outer: PeripheryXilinxVC707PCIeX1
-  val io: PeripheryXilinxVC707PCIeX1Bundle
+trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+    with HasSystemXilinxVC707PCIeX1Bundle {
+  val outer: HasSystemXilinxVC707PCIeX1
+  val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
+
+  xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
 
-  io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+  outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+  outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
 }