xilinxvc707pciex1: push to a dedicated clock domain

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1Periphery.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index 494d787a791504c4f3b2e9a941b74e677d7134b0..c994856f5b1c3b2cbffa87105cbc369323472e1a 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -3,25 +3,35 @@ package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
 import diplomacy.LazyModule
-import rocketchip.{L2Crossbar,L2CrossbarModule,L2CrossbarBundle}
-import uncore.tilelink2.TLWidthWidget
+import rocketchip.{
+  HasTopLevelNetworks,
+  HasTopLevelNetworksModule,
+  HasTopLevelNetworksBundle
+}
+import uncore.tilelink2._
 
-trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar {
+trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  l2.node := xilinxvc707pcie.master
-  xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  intBus.intnode := xilinxvc707pcie.intnode
+  private val intXing = LazyModule(new IntXing)
+
+  fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
+  xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  intBus.intnode := intXing.intnode
+  intXing.intnode := xilinxvc707pcie.intnode
 }
 
-trait PeripheryXilinxVC707PCIeX1Bundle extends L2CrossbarBundle {
+trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
   val xilinxvc707pcie = new XilinxVC707PCIeX1IO
 }
 
-trait PeripheryXilinxVC707PCIeX1Module extends L2CrossbarModule {
-  val outer: PeripheryXilinxVC707PCIeX1
-  val io: PeripheryXilinxVC707PCIeX1Bundle
+trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
+  val outer: HasPeripheryXilinxVC707PCIeX1
+  val io: HasPeripheryXilinxVC707PCIeX1Bundle
 
   io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+
+  outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+  outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
 }