import Chisel._
import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
+import rocketchip.{
+ HasTopLevelNetworks,
+ HasTopLevelNetworksModule,
+ HasTopLevelNetworksBundle
+}
import uncore.tilelink2.TLWidthWidget
-trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
+trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
- l2.node := xilinxvc707pcie.master
+ fsb.node := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
intBus.intnode := xilinxvc707pcie.intnode
}
-trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
+trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
val xilinxvc707pcie = new XilinxVC707PCIeX1IO
}
-trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
- val outer: PeripheryXilinxVC707PCIeX1
- val io: PeripheryXilinxVC707PCIeX1Bundle
+trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
+ val outer: HasPeripheryXilinxVC707PCIeX1
+ val io: HasPeripheryXilinxVC707PCIeX1Bundle
io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
}