uart: make it easy to simulate large text printouts (#33)

[sifive-blocks.git] / src / main / scala / ip / xilinx / vc707mig / vc707mig.scala

diff --git a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
index 6f281ecbaea0ce9d9015a8ac7a42f9913fc37dd3..1e01748b531eac309e5f3087149ca1fee2619587 100644 (file)
--- a/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
+++ b/src/main/scala/ip/xilinx/vc707mig/vc707mig.scala
@@ -3,8 +3,7 @@ package sifive.blocks.ip.xilinx.vc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import junctions._
+import freechips.rocketchip.config._
 
 // IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
 // Black Box
@@ -31,9 +30,8 @@ trait VC707MIGIODDR extends Bundle {
 //reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
 trait VC707MIGIOClocksReset extends Bundle {
   //inputs
-  //differential system clocks
-  val sys_clk_n             = Bool(INPUT)
-  val sys_clk_p             = Bool(INPUT)
+  //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
+  val sys_clk_i             = Bool(INPUT)
   //user interface signals
   val ui_clk                = Clock(OUTPUT)
   val ui_clk_sync_rst       = Bool(OUTPUT)