package sifive.blocks.ip.xilinx.vc707mig
import Chisel._
-import config._
-import junctions._
+import chisel3.experimental.{Analog,attach}
+import freechips.rocketchip.config._
// IP VLNV: xilinx.com:customize_ip:vc707mig:1.0
// Black Box
-// Signals named _exactly_ as per MIG generated verilog
-trait VC707MIGUnidirectionalIODDR extends Bundle {
- //outputs
+trait VC707MIGIODDR extends Bundle {
val ddr3_addr = Bits(OUTPUT,14)
val ddr3_ba = Bits(OUTPUT,3)
val ddr3_ras_n = Bool(OUTPUT)
val ddr3_cs_n = Bits(OUTPUT,1)
val ddr3_dm = Bits(OUTPUT,8)
val ddr3_odt = Bits(OUTPUT,1)
+
+ val ddr3_dq = Analog(64.W)
+ val ddr3_dqs_n = Analog(8.W)
+ val ddr3_dqs_p = Analog(8.W)
}
//reused directly in io bundle for sifive.blocks.devices.xilinxvc707mig
-trait VC707MIGUnidirectionalIOClocksReset extends Bundle {
+trait VC707MIGIOClocksReset extends Bundle {
//inputs
- //differential system clocks
- val sys_clk_n = Bool(INPUT)
- val sys_clk_p = Bool(INPUT)
+ //"NO_BUFFER" clock source (must be connected to IBUF outside of IP)
+ val sys_clk_i = Bool(INPUT)
//user interface signals
val ui_clk = Clock(OUTPUT)
val ui_clk_sync_rst = Bool(OUTPUT)
//turn off linter: blackbox name must match verilog module
class vc707mig(implicit val p:Parameters) extends BlackBox
{
- val io = new Bundle with VC707MIGUnidirectionalIODDR
- with VC707MIGUnidirectionalIOClocksReset {
- // bidirectional signals on blackbox interface
- // defined here as an output so "__inout" signal name does not have to be used
- // verilog does not check the
- val ddr3_dq = Bits(OUTPUT,64)
- val ddr3_dqs_n = Bits(OUTPUT,8)
- val ddr3_dqs_p = Bits(OUTPUT,8)
+ val io = new Bundle with VC707MIGIODDR
+ with VC707MIGIOClocksReset {
// User interface signals
val app_sr_req = Bool(INPUT)
val app_ref_req = Bool(INPUT)