X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWM.scala;h=638100496dabfb564b597a335d05e57c68aef041;hp=3d35d81cf49fcbf5a8a64bc5a07e28a9204f2611;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hpb=fe65a87c5c94466ce17896cfd896c8e7c127d79b

diff --git a/src/main/scala/devices/pwm/PWM.scala b/src/main/scala/devices/pwm/PWM.scala
index 3d35d81..6381004 100644
--- a/src/main/scala/devices/pwm/PWM.scala
+++ b/src/main/scala/devices/pwm/PWM.scala
@@ -2,6 +2,7 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import Chisel.ImplicitConversions._
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.regmapper._
@@ -48,7 +49,7 @@ trait HasPWMBundleContents extends Bundle {
   val gpio = Vec(params.ncmp, Bool()).asOutput
 }
 
-trait HasPWMModuleContents extends Module with HasRegMap {
+trait HasPWMModuleContents extends MultiIOModule with HasRegMap {
   val io: HasPWMBundleContents
   val params: PWMParams