X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPeriphery.scala;h=00043ab97abd245c014fa5cc5127e23b7de2f99f;hp=d3e1c5bc8152580001579422bff8d519fee00dae;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hpb=fe65a87c5c94466ce17896cfd896c8e7c127d79b

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index d3e1c5b..00043ab 100644
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.pwm
 import Chisel._
 import freechips.rocketchip.config.Field
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.devices.pinctrl.{Pin}
 
@@ -31,7 +31,7 @@ trait HasPeripheryPWMBundle {
 
 }
 
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))