X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fpwm%2FPWMPins.scala;h=03acc902dad5bb77c5c872395c28f3f59695f095;hp=7ab76f07a2aa429d7fa25b3cc450f7fd3ab630a9;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hpb=fe65a87c5c94466ce17896cfd896c8e7c127d79b

diff --git a/src/main/scala/devices/pwm/PWMPins.scala b/src/main/scala/devices/pwm/PWMPins.scala
index 7ab76f0..03acc90 100644
--- a/src/main/scala/devices/pwm/PWMPins.scala
+++ b/src/main/scala/devices/pwm/PWMPins.scala
@@ -4,7 +4,7 @@ package sifive.blocks.devices.pwm
 import Chisel._
 import freechips.rocketchip.config.Field
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.devices.pinctrl.{Pin}