X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fuart%2FUARTPeriphery.scala;h=d1db77b9d4ab222b10f84dc012b14e09dc52a9db;hp=95d0c3b4bdb7d7d65345f3990c1e65d9893dd723;hb=4fcf349adb9e66ea7d8cc5394de5d3e0a2340985;hpb=fe65a87c5c94466ce17896cfd896c8e7c127d79b

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 95d0c3b..d1db77b 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -5,7 +5,7 @@ import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
@@ -29,7 +29,7 @@ trait HasPeripheryUARTBundle {
 
 }
 
-trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
+trait HasPeripheryUARTModuleImp extends LazyModuleImp with HasPeripheryUARTBundle {
   val outer: HasPeripheryUART
   val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))