X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=blobdiff_plain;f=src%2Fmain%2Fscala%2Fdevices%2Fxilinxvc707pciex1%2FXilinxVC707PCIeX1Periphery.scala;h=d64d19aff9546e81dfb0f24861ec945dd0024c30;hp=f37f7f9da272b571bcbfe2bdb4e89fb951d39200;hb=e2073feef87f080ac3e354774c3a0cbb0a55be3d;hpb=c1872c574b1e471778ec28e6a782b6547e6917da

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index f37f7f9..d64d19a 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget
 trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
 
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  l2FrontendBus.node := xilinxvc707pcie.master
+  fsb.node := xilinxvc707pcie.master
   xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
   xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
   intBus.intnode := xilinxvc707pcie.intnode