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(parent: ebd3ffa) | patch
Use _chisel3 analog for MIG inout vc707_mig_analog_inout
authorHenry Styles <hes@sifive.com>
Tue, 25 Apr 2017 17:15:00 +0000 (10:15 -0700)
committerHenry Styles <hes@sifive.com>
Tue, 25 Apr 2017 17:15:00 +0000 (10:15 -0700)
commitb882d6da934b8a6f0f1780c0cedfaf54ba7701c8
tree8ad79e13bc9517f6fbfd864ab068fa3e23f55417tree
parentebd3ffa57e8f7d0706e85c0a8165942caea2aa11commit | diff
Use _chisel3 analog for MIG inout
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala diff | blob | history
src/main/scala/ip/xilinx/vc707mig/vc707mig.scala diff | blob | history
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