From: Wesley W. Terpstra <wesley@sifive.com>
Date: Tue, 31 Jan 2017 22:03:14 +0000 (-0800)
Subject: spi: work around ucb-bar/chisel3#472
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=535be3e9761218a864bb553d996296dc65ea1735

spi: work around ucb-bar/chisel3#472
---

diff --git a/src/main/scala/devices/spi/SPIConsts.scala b/src/main/scala/devices/spi/SPIConsts.scala
index b18b08a..5d6dd0d 100644
--- a/src/main/scala/devices/spi/SPIConsts.scala
+++ b/src/main/scala/devices/spi/SPIConsts.scala
@@ -5,29 +5,29 @@ import Chisel._
 
 object SPIProtocol {
   val width = 2
-  val Single = UInt(0, width)
-  val Dual   = UInt(1, width)
-  val Quad   = UInt(2, width)
+  def Single = UInt(0, width)
+  def Dual   = UInt(1, width)
+  def Quad   = UInt(2, width)
 
-  val cases = Seq(Single, Dual, Quad)
+  def cases = Seq(Single, Dual, Quad)
   def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
 }
 
 object SPIDirection {
   val width = 1
-  val Rx = UInt(0, width)
-  val Tx = UInt(1, width)
+  def Rx = UInt(0, width)
+  def Tx = UInt(1, width)
 }
 
 object SPIEndian {
   val width = 1
-  val MSB = UInt(0, width)
-  val LSB = UInt(1, width)
+  def MSB = UInt(0, width)
+  def LSB = UInt(1, width)
 }
 
 object SPICSMode {
   val width = 2
-  val Auto = UInt(0, width)
-  val Hold = UInt(2, width)
-  val Off  = UInt(3, width)
+  def Auto = UInt(0, width)
+  def Hold = UInt(2, width)
+  def Off  = UInt(3, width)
 }
diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index 6584be8..cb26bc9 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -12,8 +12,8 @@ class SPIMicroOp(c: SPIConfigBase) extends SPIBundle(c) {
 }
 
 object SPIMicroOp {
-  val Transfer = UInt(0, 1)
-  val Delay    = UInt(1, 1)
+  def Transfer = UInt(0, 1)
+  def Delay    = UInt(1, 1)
 }
 
 class SPIPhyControl(c: SPIConfigBase) extends SPIBundle(c) {