From: Alex Solomatnikov <sols@gamma06.internal.sifive.com>
Date: Mon, 6 Feb 2017 18:39:47 +0000 (-0800)
Subject: Renamed i2cDevices to i2c
X-Git-Url: https://git.libre-soc.org/?p=sifive-blocks.git;a=commitdiff_plain;h=5a0d084b3867dd6494974bf12a139eb98810c2e4

Renamed i2cDevices to i2c
---

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index 7ee5015..09bb9cc 100644
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -8,7 +8,7 @@ import uncore.tilelink2.TLFragmenter
 
 trait PeripheryI2C {
   this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
-  val i2cDevices = i2cConfigs.zipWithIndex.map { case (c, i) =>
+  val i2c = i2cConfigs.zipWithIndex.map { case (c, i) =>
     val i2c = LazyModule(new TLI2C(c))
     i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := i2c.intnode
@@ -27,7 +27,7 @@ trait PeripheryI2CModule {
     val outer: PeripheryI2C
     val io: PeripheryI2CBundle
   } =>
-  (io.i2cs zip outer.i2cDevices).foreach { case (io, device) =>
+  (io.i2cs zip outer.i2c).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }